2nm is the Next Big Thing in chip production, and Synopsys design tools and IP are now ready for production work and tape-outs on Samsung’s latest fab.
Samsung has its eyes on the prize, hoping to secure more design wins as it competes with TSMC for the semiconductor industry’s transition to 2nm fabrication. The company is expected to announce details about its Gate All Around SF2 2nm process at a session on June 19 at the VLSI Symposium. Chip designers will be pleased to hear that Synopsys is now ready for SF2, and has certified its AI-driven analog and digital design flows for the next generation fabrication process. Synopsys has announced that it and Samsung have collaborated on design techniques for SF2, including backside power and nanosheet optimization to deliver more efficient power distribution.
Synopsys has also readied its ASO.ai tool to enable analog design elements to quickly migrate to SF2 with the help of AI. For multi-die chip designs, Synopsys has certified its 3DIC Compiler and UCIe IP blocks for building silicon and connecting chiplets. Finally, Synopsys has readied its IP portfolio, which chip designers use for things like Phys and PCIe blocks, to be included in chip designs and tape-outs for SF2.
Chips built on SF2 are expected to roll out in 2025, typically led by designs for the massive mobile smartphone market. A report from Business Korea stated that Samsung SF2 will be used to power the Samsung Exynos 2600 andSee A Total Eclipse Of A Star As Manhattanhenge Returns The Night Sky This WeekSynopsys claims the industry’s broadest portfolio of certified IP products for Samsung fabrication, including USB 3.2, eUSB2, MIPI PHYs, and a range of PCIe blocks.